DRAM predominantly has memory cells each including a single MOS transistor and a single capacitor. In such a one-transistor/one-capacitor type DRAM as the above, as high integration and miniaturization are demanded therefor in these years, stack type capacitor has been employed in place of conventional planar type one in order to compensate for the lack of the intended capacitance of the capacitor caused by a corresponding reduction in the area of memory cells. FIG. 13 shows a cross-sectional view of a part of conventional DRAM memory cells having the aforementioned stack type capacitors, in which a left side in the drawing denotes transistors for addressing of DRAM memory cells and a right side therein denotes transistors for addressing memory cells (which addressing is for column selection).
A group of M0S transistors 105 shown in the left side of FIG. 13 are formed in the following manner. A group of gate electrodes 104 arranged in a matrix form is first formed through a gate oxide film (not shown) on a P type silicon substrate 101 having an inter-element separation region 151 formed therein. Then areas of the substrate 101 located at both sides of the gate electrode group 104 are subjected to an ion implanting operation with use of, e.g., phosphorus to thereby form a plurality of pairs of impurity diffused regions 102 and 103 as source/drain regions.
A group of stack type capacitors 106 forming the DRAM memory cells together with the MOS transistor group 105 each includes a lower electrode 107 having a polycrystalline silicon film containing an impurity, a dielectric film 108 made of, e.g., a silicon oxide film or a 3-layered structure of an oxide layer, a nitride layer and an oxide layer, and an upper electrode 109 provided opposite to the lower electrode 107 with the dielectric film 108 interposed therebetween and having a polycrystalline silicon film containing an impurity. Connected to the lower electrode 107 of the capacitor group 106 is one impurity diffused region 102 of the corresponding MOS transistor in the MOS transistor group 105.
The MOS transistor group 105 and capacitor group 106 are covered with an insulating film 110 such as a boron phosphor silicon glass (BPSG) film. A wiring 111 for fixing a potential of the upper electrode 109 of the capacitor group 106 is connected to the upper electrode 109 of the capacitor group 106 at a contact hole 110a made in the insulating film 110.
Meanwhile, as shown on the right side in FIG. 13, one impurity diffused region 113 of a transistor 112 for column selection of memory cells formed simultaneously with the formation of the MOS transistor group 105, is connected to a wiring (bit line) 118 formed differently from the wiring 111 at a contact hole 110b made in the insulating films 110 and 119. The wiring 118 in turn is connected to the other impurity diffused region 103 of the MOS transistor group 105 (, which connection is not shown). Further sequentially formed on the wirings 111 and 118 are an inter-layer insulating film 114, word lines 115, an insulating film 116 and a protective film 117. Each of the word lines 115 is connected to the associated gate electrode of the gate electrode group 104 in the MOS transistor group 105 and also to a decoder (not shown).
With the DRAM having a structure as mentioned above, since interconnection between the wiring 111 and upper electrode 109 is established by means of the contact hole 110a made in the insulating film 110 on the capacitor 106, an aspect ratio of the contact hole 110b for interconnection between one impurity diffused region 113 of the transistor 112 for column selection of memory cells and the wiring 118 becomes large, that is, the contact hole 110b becomes deep. This involves the problem that coverage of the wiring 118 at the bottom of the contact hole 110b becomes poor and thus it becomes impossible to form the wiring 118 with a high reliability.
Meanwhile, there has been studied in these years a method in which a capacitor dielectric film for DRAM memory cells is made of a material having a high dielectric constant or permittivity to compensate for the lack of the intended capacitance of the capacitor caused by a corresponding reduction in the area of memory cells. This method, however, involves another problem that the above dielectric material, which is different in property from silicon, causes interdiffusion with silicon at a temperature of, e.g., over 700.degree. C. to deteriorate the element characteristics. In the above prior art DRAM fabricating process, the dielectric film 108 is formed and thereafter thermal annealing operations including the reflowing the BPSG film 110 and the activation of the contact of the contact hole 110b after the implantation are carried out at a temperature of over 700.degree. C. Therefore, it has conventionally been difficult to employ a material having a high dielectric constant as a capacitor dielectric film.
In order to prevent the interdiffusion between the capacitor dielectric film of the material with the high dielectric constant and the upper and lower electrodes of the capacitor, it is also considered for the material of these electrodes to be made of electrically conductive oxide material such as ruthenium dioxide. In this case, however, the problem occurs that interdiffusion takes place between the conductive oxide such as ruthenium dioxide and the silicon substrate 101 during the thermal annealing.
Besides this, it is necessary that the bit wiring 118 of the transistors for column selection be formed only after the wiring 111 is formed and then the insulating film 119 covering the wiring 111 is formed on the silicon substrate 101. Further, for the purpose of eliminating an error in resist dimensions in a photo-lithographical technique, it is necessary to flatten the insulating films 110 and 119. However, this causes the problem that the number of steps for fabricating the semiconductor memory device is increased.